87.xilinx FPGA读取器件id方法

 dout数据高位先出msb

module chip_id_reader(input clk,input reset,output [56:0] dna_value,output dna_valid
);reg [6:0] bit_count;reg [56:0] dna_shift_reg;reg dna_read;reg dna_shift;wire dna_out;// 实例化DNA_PORT原语DNA_PORT #(.SIM_DNA_VALUE(57'h123456789ABCDEF)  // 仅用于仿真) dna_port_inst (.DOUT(dna_out),.CLK(clk),.DIN(1'b0),.READ(dna_read),.SHIFT(dna_shift));// 控制状态机always @(posedge clk or posedge reset) beginif(reset) beginbit_count <= 0;dna_read <= 1'b1;dna_shift <= 1'b0;dna_shift_reg <= 57'd0;endelse beginif(bit_count == 0) begindna_read <= 1'b0;dna_shift <= 1'b1;bit_count <= bit_count + 1;endelse if(bit_count < 58) begindna_shift_reg <= {dna_shift_reg[55:0], dna_out};bit_count <= bit_count + 1;endelse begindna_shift <= 1'b0;endendendassign dna_valid = (bit_count == 58);assign dna_value = dna_shift_reg;
endmodule